1. Field of the Invention
This invention is related to the field of processors and, more particularly, to addressing memory operands in processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
The x86 architecture specifies a variable length instruction set (i.e. the size of the various instructions in the instruction set may differ). By providing variable length instructions, each instruction occupies only the amount of memory needed to specify that instruction and any operands thereof. For example, the x86 architecture specifies an instruction set having instructions anywhere from 1 byte to 15 bytes in length. Thus, the amount of memory occupied by a code sequence may be more optimal, as compared to fixed length instruction sets which tend to occupy more memory. In other words, the code density (number of instructions/unit memory) may be higher for variable length instruction sets than for fixed length instruction sets for a given code sequence. Not only is the efficient use of memory possible, but delays in fetching the instructions from memory may be, on average, lower since a given set of bytes fetched from memory may include more variable byte length instructions than fixed length instructions.
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes. Thus, it may be desirable to provide an architecture which is compatible with the x86 processor architecture but which includes support for 64 bit processing as well.
Unfortunately, extending the x86 processor architecture to 64 bits may be problematic. For example, xe2x80x9cstatic variablesxe2x80x9d may typically be accessed using instructions having displacement-only addressing (in which the displacement is the effective address of the variable). Generally, static variables are variables whose locations are assigned during a build of the code sequence accessing the variables and thus are addressable using a fixed value in the displacement field. Static variables may include xe2x80x9cglobal variablesxe2x80x9d (variables accessed by several different code sequences or different routines in the same code sequence). Additionally, static variables may include local variables that a particular code sequence requires to be persistent across different calls to the code sequence.
To provide for arbitrary placement of such static variables in memory and to still access them using displacement-only addressing, displacements would have to be increased to 64 bits (8 bytes) in such instructions. Code density would be negatively impacted. If displacements are not increased, then either static variables would be limited to placement in the lowest-addressed four gigabytes of memory (the memory addressable with a 32 bit effective address) or a general purpose register (EAX, etc.) would be required to address the static variables, increasing the pressure on the limited number of general purpose registers in the x86 register set. Still further, the use of displacement-only addressing leads to less position independence of the corresponding code sequences, since displacement-only addressing produces an absolute address.
One prior art proposed solution to the above is to redefine the following x86 encoding to indicate instruction pointer (IP) relative addressing (e.g. using a displacement and the instruction pointer as address operands) rather than displacement-only addressing: (i) the addressing mode byte (ModRIM) encoding of mod field=01 or 11 (in binary), r/m field=100 (in binary); and (ii) the SIB byte encoding of base=101 (in binary), index=100 (in binary). The ModR/M encoding indicates that the scale-index-base (SIB) byte follows, and the SIB encoding previously indicated only the displacement as an address operand. Other index encodings could be used to provide indexed WP-relative addressing. Another prior art proposed solution includes using the same encoding as (i) and (ii) above but with the base encoding being expanded by a bit and being equal to 1101 (in binary).
A processor is described which supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an operating mode or modes in which the address size is greater than 32 bits (e.g. up to 64 bits). In some embodiments, the displacement may be limited to less than the address size (e.g. 32 bits, in one implementation) when such operating modes are active. Code density may be higher than if the displacements were expanded, and flexibility in the placement of variables in memory may be achieved. For example, static variables may be placed in memory with flexibility, and IP relative addressing may be used to locate the static variables. Furthermore, position-independence of the code may be increased using IP-relative addressing instead of displacement-only addressing.
Broadly speaking, a processor is contemplated. The processor comprises a register configured to store an instruction pointer; and an execution core coupled to receive the instruction pointer, an instruction, and an operating mode indication indicative of one of a plurality of operating modes of the processor. The execution core is configured, responsive to a first encoding of an addressing mode byte of the instruction and a first operating mode of the plurality of operating modes, to include the instruction pointer as an address operand of the instruction. The execution core is also configured, responsive to a second operating mode of the plurality of operating modes and the first encoding, to include only a displacement as the address operand of the instruction.
Additionally, an apparatus is contemplated comprising a storage location for storing an instruction pointer and a processor coupled to the storage location. The processor is configured, responsive to a first encoding of an addressing mode byte of an instruction and a first operating mode of a plurality of operating modes, to include the instruction pointer as an address operand of the instruction. The processor is also configured, responsive to a second operating mode of the plurality of operating modes and the first encoding, to include only a displacement as the address operand of the instruction.
Moreover, a method is contemplated. An instruction pointer is included as an address operand of an instruction responsive to a first encoding of an addressing mode byte of the instruction and a first operating mode of a plurality of operating modes of a processor. Only a displacement is included as the address operand of the instruction responsive to the first encoding of the addressing mode byte and a second operating mode of the plurality of operating mode.